As the feature size in integrated circuits continues to shrink the gate size for transistors must be correspondingly reduced. In state of the art III-V transistor devices the gate size has reached the point where gate resistance due to the small gate dimensions is a performance limiting factor. To overcome this limitation T-shaped gates and Y-shaped gates have been proposed. See e.g. M. H. Somerville et al "A model for Tunneling-Limited Breakdown in High Power HEMTs", IEEE IEDM, pp. 35-38 (1996); F. Ren et aL, "Y-gate submicron gate length GaAs metal-semiconductor field effect transistors", J. Vac. Sci. Technol. B 11(5), September/October 1993; A. Mahajan et al, "Monolithic Integration of InAlAs/InGaAs/InP Enhancement- and Depletion-Mode High Electron Mobility Transistors, IEEE IEDM, pp. 51-53, (1996). The T-shaped electrodes for these devices are produced by exposing T-shaped patterns in the resist at the gate location, developing the resist to form T-shaped openings, and evaporating metal into the T-shaped openings. A lift-off process is used to remove excess metal on the resist surface between T-shaped features. The e-beam approach has been successful but the e-beam writing step to form the T-shaped features is slow due to that characteristic raster scan of e-beam lithography, and very expensive. A better approach from the standpoint of throughput would be to use the blanket exposure characteristic of photolithographic processes but to date a photolithographic process for forming a vertically oriented T-shaped feature has not been available in the context of this technology.